The disclosed embodiments of the present invention relate to video data processing, and more particularly, to a video transmitting system with on-the-fly encoding and on-the-fly delivering and an associated video receiving system.
According to one conventional video processing design, a frame-based pipeline structure may be employed. Regarding a video transmitting system, the pipeline stages may include a video encoder and a transmitting circuit. However, the video encoder does not start encoding a video frame until pixel data of the video frame is fully received, and the transmitting circuit does not start outputting a video bitstream of an encoded video frame until encoded pixel data of a video frame is fully generated. Regarding a video receiving system, the pipeline stages may include a video decoder and a display circuit. However, the video decoder does not start decoding a video bitstream of an encoded video frame until encoded pixel data of a video frame is fully received, and the display circuit does not start driving a display device to show a video frame until decoded pixel data of the video frame is fully generated. The conventional frame-based pipeline structure may fail to meet the requirements of some ultra-low latency applications due to long latency between pipeline stages. Thus, there is a need for an innovative ultra-low latency video transmitting system design and an ultra-low latency video receiving system design.